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1/18 l6205 april 2002 n operating supply voltage from 8 to 52v n 5.6a output peak current (2.8a dc) n r ds(on) 0.3 w typ. value @ t j = 25 c n operating frequency up to 100khz n non dissipative overcurrent protection n paralleled operation n cross conduction protection n thermal shutdown n under voltage lockout n integrated fast free wheeling diodes typical applications n bipolar stepper motor n dual or quad dc motor description the l6205 is a dmos dual full bridge designed for motor control applications, realized in multipower- bcd technology, which combines isolated dmos power transistors with cmos and bipolar circuits on the same chip. available in powerdip20 (16+2+2), powerso20 and so20(16+2+2) packages, the l6205 features a non-dissipative protection of the high side powermosfets and thermal shutdown. block diagram d99in1091a gate logic over current detection over current detection gate logic vcp vboot en a in1 a in2 a en b in1 b in2 b v boot 5v 10v vs a v s b out1 a out2 a out1 b out2 b sense a charge pump voltage regulator thermal protection v boot v boot 10v 10v bridge a bridge b sense b ocd a ocd b ordering numbers: l6205n (powerdip20) L6205PD (powerso20) l6205d (so20) powerdip20 (16+2+2) powerso20 so20 (16+2+2) dmos dual full bridge driver
l6205 2/18 absolute maximum ratings recommended operating conditions symbol parameter test conditions value unit v s supply voltage 60 v v in ,v en input and enable voltage range -0.3 to +7 v v sense dc sensing voltage range -1 to +4 v v boot bootstrap peak voltage v s + 10 v i s(peak) pulsed supply current (for each vs pin), internally limited by the overcurrent protection t pulse < 1ms 7.1 a i s dc supply current (for each vs pin) 2.8 a v od differential voltage between vs a , out1 a , out2 a , sense a and vs b , out1 b , out2 b , sense b vs a = vs b = 60v sense a = sense b = gnd 60 v t stg , t op storage and operating temperature range -40 to 150 c symbol parameter min max unit v s supply voltage 12 52 v v od differential voltage between vs a , out1 a , out2 a , sense a and vs b , out1 b , out2 b , sense b 52 v v sense sensing voltage (pulsed tw 3/18 l6205 thermal data pin connections (top view) symbol description powerdip20 so20 powerso20 unit r th-j-pins maximumthermal resistance junction-pins 12 14 - c/w r th-j-case maximum thermal resistance junction-case - - 1 c/w r th-j-amb1 maximumthermal resistance junction-ambient 1 <1> mounted on a multilayer fr4 pcb with a dissipating copper surface on the bottom side of 6 cm 2 (with a thickness of 35 m). 40 51 - c/w r th-j-amb1 maximum thermal resistance junction-ambient 2 <2> mounted on a multilayer fr4 pcb with a dissipating copper surface on the top side of 6 cm 2 (with a thickness of 35 m). --35 c/w r th-j-amb1 maximumthermal resistance junction-ambient 3 <3> mounted on a multilayer fr4 pcb with a dissipating copper surface on the top side of 6 cm 2 (with a thickness of 35 m), 16 via holes and a ground layer. --15 c/w r th-j-amb2 maximum thermal resistance junction-ambient 4 <4> mounted on a multilayer fr4 pcb without any heat sinking surface on the board. 56 77 62 c/w gnd out1 a sense a in2 a in1 a vcp en a out2 a vs a vs b out2 b vboot in2 b en b in1 b sense b out1 b gnd 10 8 9 7 6 5 4 3 2 13 14 15 16 17 19 18 20 12 1 11 gnd gnd d99in1092a gnd out1 b sense b in1 b in2 b 1 3 2 4 5 6 7 8 9 en b vboot out2 b vs b gnd 15 14 13 12 11 d99in1093a 10 20 19 18 17 16 in1 a in2 a sense a out1 a gnd gnd vs a out2 a vcp en a powerdip20/so20 powerso20
l6205 4/18 (*) also connected at the output drain of the overcurrent and thermal protection mosfet. therefore, it has to be driven putting in series a resistor with a value in the range of 500 w - 22k w , recommended 10k w pin description package name type function so20/ powerdip20 powerso20 pin # pin # 1 6 in1 a logic input bridge a logic input 1. 2 7 in2 a logic input bridge a logic input 2. 3 8 sense a power supply bridge a source pin. this pin must be connected to power ground directly or through a sensing power resistor. 4 9 out1 a power output bridge a output 1. 5, 6, 15, 16 1, 10, 11, 20 gnd gnd signal ground terminals. in powerdip and so packages, these pins are also used for heat dissipation toward the pcb. 7 12 out1 b power output bridge b output 1. 8 13 sense b power supply bridge b source pin. this pin must be connected to power ground directly or through a sensing power resistor. 9 14 in1 b logic input bridge b logic input 1. 10 15 in2 b logic input bridge b logic input 2. 11 16 en b logic input (*) bridge b enable. low logic level switches off all power mosfets of bridge b. this pin is also connected to the collector of the overcurrent and thermal protection transistor to implement over current protection. if not used, it has to be connected to +5v through a resistor. 12 17 vboot supply voltage bootstrap voltage needed for driving the upper powermosfets of both bridge a and bridge b. 13 18 out2 b power output bridge b output 2. 14 19 vs b power supply bridge b power supply voltage. it must be connected to the supply voltage together with pin vs a . 17 2 vs a power supply bridge a power supply voltage. it must be connected to the supply voltage together with pin vs b . 18 3 out2 a power output bridge a output 2. 19 4 vcp output charge pump oscillator output. 20 5 en a logic input (*) bridge a enable. low logic level switches off all power mosfets of bridge a. this pin is also connected to the collector of the overcurrent and thermal protection transistor to implement over current protection. if not used, it has to be connected to +5v through a resistor.
5/18 l6205 electrical characteristics (t amb = 25 c, v s = 48v, unless otherwise specified) symbol parameter test conditions min typ max unit v s supply voltage 8 52 v i s quiescent supply current all bridges off; -25c l6205 6/18 <(5)> see fig. 1. figure 1. switching characteristic definition i inl low level logic input current gnd logic input voltage -10 m a over current protection i s over input supply over current protection threshold -25c 7/18 l6205 circuit description power stages and charge pump the l6205 integrates two independent power mos full bridges. each power mos has an rd- son=0.3ohm (typical value @25c), with intrinsic fast freewheeling diode. cross conduction protection is achieved using a dead time (td = 1 m s typical) be- tween the switch off and switch on of two power mos in one leg of a bridge. using n channel power mos for the upper transis- tors in the bridge requires a gate drive voltage above the power supply voltage. the bootstrapped (vboot) supply is obtained through an internal oscillator and few external components to realize a charge pump circuit as shown in figure 2. the oscillator output (vcp) is a square wave at 750khz (typical) with 10v amplitude. recommended values/part numbers for the charge pump circuit are shown in table1. table 1. charge pump external components values figure 2. charge pump circuit logic inputs pins in1 a , in2 a , in1 b and in2 b are ttl/cmos and m c compatible logic inputs. the internal structure is shown in fig. 3. typical value for turn-on and turn-off thresholds are respectively vthon=1.8v and vthoff=1.3v. pins en a and en b have identical input structure with the exception that the drains of the overcurrent and thermal protection mosfets (one for the bridge a and one for the bridge b) are also connected to these pins. due to these connections some care needs to be taken in driving these pins. the en a and en b in- puts may be driven in one of two configurations as shown in figures 4 or 5. if driven by an open drain (collector) structure, a pull-up resistor r en and a ca- pacitor c en are connected as shown in fig. 4. if the driver is a standard push-pull structure the resistor r en and the capacitor c en are connected as shown in fig. 5. the resistor r en should be chosen in the range from 500 w to 22k w . recommended values for r en and c en are respectively 10k w and 100nf. more information on selecting the values is found in the overcurrent protection section. figure 3. logic inputs internal structure figure 4. en a and en b pins open collector driving figure 5. en a and en b pins push-pull driving truth table x = don't care high z = high impedance output c boot 220nf c p 10nf r p 100 w d1 1n4148 d2 1n4148 d2 c boot d1 r p c p v s vs a vcp vboot vs b d01in1328 inputs outputs en in1 in2 out1 out2 l x x high z high z h l l gnd gnd h h l vs gnd hlhgndvs hhhvsvs 5v d01in1329 5v 5v open collector output r en c en en a or en b d02in134 9 5v push-pull output r en c en en a or en b d02in135 0
l6205 8/18 non-dissipative overcurrent protection in addition to the pwm current control, an overcurrent detection circuit (ocd) is integrated for full protection. this circuit provides protection against a short circuit to ground or between two phases of the bridge. with this internal over current detection, the external current sense resistor normally used and its associated power dis- sipation are eliminated. figure 6 shows a simplified schematic of the overcurrent detection circuit for the bridge a. bridge b is provided of an analogous circuit. to implement the over current detection, a sensing element that delivers a small but precise fraction of the out- put current is implemented with each high side power mos. since this current is a small fraction of the output current there is very little additional power dissipation. this current is compared with an internal reference cur- rent i ref . when the output current reaches the detection threshold (typically 5.6a) the ocd comparator signals a fault condition. when a fault condition is detected, the en pin is pulled below the turn off threshold (1.3v typ- ical) by an internal open drain mos with a pull down capability of 4ma. by using an external r-c on the en pin, the off time before recovering normal operation can be easily programmed by means of the accurate thresholds of the logic inputs. figure 7 shows the ocd operation. figure 6. overcurrent protection simplified schematic figure 7. overcurrent protection waveforms + over temperature i ref (i 1a +i 2a ) / n i 1a / n power sense 1 cell power sense 1 cell power dmos n cells power dmos n cells high side dmoss of the bridge a out1 a out2 a vs a i 1a i 2a i 2a / n ocd comparator to gate logic internal open-drain r ds(on) 60 w typ. c en r en en a +5v m c or logic d02in1353 t d(off) v dd 5.6a v th on t disable i outa (or b) v ena (orb) bridgea (or b) on off
9/18 l6205 application information a typical application using l6205 is shown in fig. 8. typical component values for the application are shown in table 2. a high quality ceramic capacitor in the range of 100 to 200 nf should be placed between the power pins (vs a and vs b ) and ground near the l6205 to improve the high frequency filtering on the power supply and reduce high frequency transients generated by the switching. the capacitors connected from the en a and en b inputs to ground set the shut down time for the brgidge a and bridge b respectively when an over current is detected (see overcurrent protection). the two current sources (sense a and sense b ) should be connected to power ground with a trace length as short as possible in the layout. to increase noise immunity, unused logic pins (except en a and en b ) are best connected to 5v (high logic level) or gnd (low logic level) (see pin description). it is recommended to keep power ground, signal ground and charge pump ground (low side of c boot capacitor) separated on pcb. table 2. component values for typical application figure 8. typical application c 1 100uf d 1 1n4148 c 2 100nf d 2 1n4148 c boot 220nf r ena 2k2 w c p 10nf r enb 2k2 w c ena 100nf r p 100 w c enb 100nf out1 a 4 18 16 15 7 13 out2 a gnd gnd gnd gnd out2 b out1 b vs a power ground signal ground + - vs 8-52v dc vs b vcp vboot c p c boot r p d 2 d 1 c 1 c 2 sense a 17 6 5 en b c enb r enb enable b 11 14 3 12 19 sense b load a load b 8 en a c ena r ena enable a 20 d02in1345 1 in1 a in2 a in1 a in2 a 2 in2 b 10 in1 b in2 b in1 b 9
l6205 10/18 paralleled operation the outputs of the l6205 can be paralleled to increase the output current capability or reduce the power dissi- pation in the device at a given current level. it must be noted, however, that the internal wire bond connections from the die to the power or sense pins of the package must carry current in both of the associated half bridges. when the two halves of one full bridge (for example out1 a and out2 a ) are connected in parallel, the peak current rating is not increased since the total current must still flow through one bond wire on the power supply or sense pin. in addition, the over current detection senses the sum of the current in the upper devices of each bridge (a or b) so connecting the two halves of one bridge in parallel does not increase the over current detec- tion threshold. for most applications the recommended configuration is half bridge 1 of bridge a paralleled with the half bridge 1 of the bridge b, and the same for the half bridges 2 as shown in figure 9. the current in the two devices connected in parallel will share very well since the r ds(on) of the devices on the same die is well matched. in this configuration the resulting bridge has the following characteristics. - equivalent device: full bridge - r ds(on) 0.15 w typ. value @ t j = 25c - 5.6a max rms load current - 11.2a ocd threshold figure 9. parallel connection for higher current to operate the device in parallel and maintain a lower over current threshold, half bridge 1 and the half bridge 2 of the bridge a can be connected in parallel and the same done for the bridge b as shown in figure 10. in this configuration, the peak current for each half bridge is still limited by the bond wires for the supply and sense pins so the dissipation in the device will be reduced, but the peak current rating is not increased. this configu- ration, the resulting bridge has the following characteristics. - equivalent device: full bridge - r ds(on) 0.15 w typ. value @ t j = 25c - 2.8a max rms load current - 5.6a ocd threshold out1 a 4 7 16 15 18 13 out1 b gnd gnd gnd gnd out2 b out2 a vs a power ground signal ground + - vs 8-52v dc vs b vcp vboot c p c boot r p d 2 d 1 c 1 c 2 sense a 17 6 5 en b 11 14 3 12 19 sense b load 8 en a c en r en en 20 d02in1359 1 in2 in1 a in2 b 10 in1 b 9 in2 a in1 2
11/18 l6205 figure 10. parallel connection with lower overcurrent threshold it is also possible to parallel the four half bridges to obtain a simple half bridge as shown in fig. 11 the resulting half bridge has the following characteristics. - equivalent device: half bridge - r ds(on) 0.075 w typ. value @ t j = 25c - 5.6a max rms load current - 11.2a ocd threshold figure 11. paralleling the four half bridges out1 a 4 18 16 15 7 13 out2 a gnd gnd gnd gnd out2 b out1 b vs a power ground signal ground + - vs 8-52v dc vs b vcp vboot c p c boot r p d 2 d 1 c 1 c 2 sense a 17 6 5 14 3 12 19 sense b load 8 d02in1360 10 in a in2 b in2 a 2 in1 a 1 in1 b in b 9 en b en a c en r en en 11 20 out1 a 4 7 16 15 18 13 out1 b gnd gnd gnd gnd out2 b out2 a vs a power ground signal ground + - vs 8-52v dc vs b vcp vboot c p c boot r p d 2 d 1 c 1 c 2 sense a 17 6 5 en b 11 14 3 12 19 sense b 8 en a c en r en en 20 d02in1366 1 in1 a in2 b 10 in1 b 9 in2 a 2 load in
l6205 12/18 output current capability and ic power dissipation in fig. 12 and fig. 13 are shown the approximate relation between the output current and the ic power dissipa- tion using pwm current control driving two loads, for two different driving types: C one full bridge on at a time (fig. 12) in which only one load at a time is energized. C two full bridges on at the same time (fig. 13) in which two loads at the same time are energized. for a given output current and driving type the power dissipated by the ic can be easily evaluated, in order to establish which package should be used and how large must be the on-board copper dissipating area to guar- antee a safe operating junction temperature (125c maximum). figure 12. ic power dissipation versus output current with one full bridge on at a time. figure 13. ic power dissipation versus output current with two full bridges on at the same time. thermal management in most applications the power dissipation in the ic is the main factor that sets the maximum current that can be de- liver by the device in a safe operating condition. therefore, it has to be taken into account very carefully. besides the available space on the pcb, the right package should be chosen considering the power dissipation. heat sinking can be achieved using copper on the pcb with proper area and thickness. figures 15, 16 and 17 show the junction-to- ambient thermal resistance values for the powerso20, powerdip20 and so20 packages. for instance, using a powerso package with copper slug soldered on a 1.5 mm copper thickness fr4 board with 6cm 2 dissipating footprint (copper thickness of 35m), the r th j-amb is about 35c/w. fig. 14 shows mount- ing methods for this package. using a multi-layer board with vias to a ground plane, thermal impedance can be reduced down to 15c/w. no pwm f sw = 30 khz (slow decay) test conditions: supply voltage = 24v i a i b i out i out 0 0.5 1 1.5 2 2.5 3 0 2 4 6 8 10 p d [w] i out [a] one full bridge on at a time no pwm f sw = 30 khz (slow decay) test conditions: supply voltage = 24v i a i b i out i out 00.511.522.5 3 0 2 4 6 8 10 p d [w ] i out [a ] two full bridges on at the same time
13/18 l6205 figure 14. mounting the powerso package. figure 15. powerso20 junction-ambient thermal resistance versus on-board copper area. figure 16. powerdip20 junction-ambient thermal resistance versus on-board copper area. figure 17. so20 junction-ambient thermal resistance versus on-board copper area. slug soldered to pcb with dissipating area slug soldered to pcb with dissipating area plus ground layer slug soldered to pcb with dissipating area plus ground layer contacted through via holes 13 18 23 28 33 38 43 12345678910111213 without ground layer with ground layer with ground layer+16 via holes sq. cm oc / w on-board copper area 39 40 41 42 43 44 45 46 47 48 49 1 2 3 4 5 6 7 8 9 101112 copper area is on bottom side copper area is on top side s q. cm oc / w on-board copper area 48 50 52 54 56 58 60 62 64 66 68 123456789101112 copper area is on top side sq. cm oc / w on-board copper area
l6205 14/18 figure 18. typical quiescent current vs. supply voltage figure 19. normalized typical quiescent current vs. switching frequency figure 20. typical low-side r ds(on) vs. supply voltage figure 21. typical high-side rds(on) vs. supply voltage figure 22. normalized r ds(on) vs.junction temperature (typical value) figure 23. typical drain-source diode forward on characteristic 4.6 4.8 5.0 5.2 5.4 5.6 0 102030405060 iq [ma] v s [v] f sw = 1khz t j = 25c t j = 85c t j = 125c 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 0 20406080100 iq / (iq @ 1 khz) f sw [khz] 0.276 0.280 0.284 0.288 0.292 0.296 0.300 0 5 10 15 20 25 30 r ds(on) [ w ] v s [v] t j = 25c 0.336 0.340 0.344 0.348 0.352 0.356 0.360 0.364 0.368 0.372 0.376 0.380 0 5 10 15 20 25 30 r ds(on) [ w ] v s [v] t j = 25c 0.8 1.0 1.2 1.4 1.6 1.8 0 20 40 60 80 100 120 140 r ds(on) / (r ds(on) @ 25 c) tj [c] 0.0 0.5 1.0 1.5 2.0 2.5 3.0 700 800 900 1000 1100 1200 1300 i sd [a] v sd [mv] t j = 25c
15/18 l6205 outline and mechanical data e a2 a e a1 pso20mec detail a t d 110 11 20 e1 e2 h x 45 detail a lead slug a3 s gage plane 0.35 l detail b r detail b (coplanarity) gc - c - seating plane e3 b c n n h bottom view e3 d1 dim. mm inch min. typ. max. min. typ. max. a 3.6 0.142 a1 0.1 0.3 0.004 0.012 a2 3.3 0.130 a3 0 0.1 0.000 0.004 b 0.4 0.53 0.016 0.021 c 0.23 0.32 0.009 0.013 d (1) 15.8 16 0.622 0.630 d1 9.4 9.8 0.370 0.386 e 13.9 14.5 0.547 0.570 e 1.27 0.050 e3 11.43 0.450 e1 (1) 10.9 11.1 0.429 0.437 e2 2.9 0.114 e3 5.8 6.2 0.228 0.244 g 0 0.1 0.000 0.004 h 15.5 15.9 0.610 0.626 h 1.1 0.043 l 0.8 1.1 0.031 0.043 n 8? (typ.) s 8? (max.) t 10 0.394 (1) d and e1 do not include mold flash or protusions. - mold flash or protusions shall not exceed 0.15mm (0.006) - critical dimensions: e, g and a3. powerso20 0056635 jedec mo-166 weight: 1.9gr
l6205 16/18 dim. mm inch min. typ. max. min. typ. max. a1 0.51 0.020 b 0.85 1.40 0.033 0.055 b 0.50 0.020 b1 0.38 0.50 0.015 0.020 d 24.80 0.976 e 8.80 0.346 e 2.54 0.100 e3 22.86 0.900 f 7.10 0.280 i 5.10 0.201 l 3.30 0.130 z 1.27 0.050 powerdip 20 outline and mechanical data
17/18 l6205 11 0 11 20 a e b d e l k h a1 c so20mec h x 45? so20 dim. mm inch min. typ. max. min. typ. max. a 2.35 2.65 0.093 0.104 a1 0.1 0.3 0.004 0.012 b 0.33 0.51 0.013 0.020 c 0.23 0.32 0.009 0.013 d 12.6 13 0.496 0.512 e 7.4 7.6 0.291 0.299 e 1.27 0.050 h 10 10.65 0.394 0.419 h 0.25 0.75 0.010 0.030 l 0.4 1.27 0.016 0.050 k 0? (min.)8? (max.) outline and mechanical data
information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is a registered trademark of stmicroelectronics a 2002 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan -malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states. http://www.st.com 18/18 l6205

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